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Challenges of SiC MOSFET Power Cycling Methodology

dc.contributor.authorGöthner, Fredrik T. B. W.
dc.contributor.authorSpro, Ole Christian
dc.contributor.authorHernes, Magnar
dc.contributor.authorPeftitsis, Dimosthenis
dc.date.accessioned2019-01-28T09:14:38Z
dc.date.available2019-01-28T09:14:38Z
dc.date.created2018-12-04T09:47:07Z
dc.date.issued2018
dc.identifier.citation20th European Conference on Power Electronics and Applications 2018nb_NO
dc.identifier.isbn978-9-0758-1528-3
dc.identifier.urihttp://hdl.handle.net/11250/2582542
dc.description.abstractThis paper investigates the power cycling methodology for reliability testing of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). Dedicated test benches were designed and built to study this issue. The results indicate that power cycling of SiC MOSFETs is affected by threshold voltage instability. A proposal for reducing the influence of the latter is also given. This is done by adding an additional gate pulse to the device under test, in order to achieve an average bias of zero during one cycle of the power cycling experiment.nb_NO
dc.description.abstractChallenges of SiC MOSFET Power Cycling Methodologynb_NO
dc.language.isoengnb_NO
dc.publisherIEEEnb_NO
dc.relation.ispartof20th European Conference on Power Electronics and Applications 2018
dc.rightsNavngivelse 4.0 Internasjonal*
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internasjonal*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/deed.no*
dc.titleChallenges of SiC MOSFET Power Cycling Methodologynb_NO
dc.typeChapternb_NO
dc.typePeer reviewednb_NO
dc.description.versionsubmittedVersionnb_NO
dc.identifier.cristin1638774
cristin.unitcode7548,50,0,0
cristin.unitnameEnergisystemer
cristin.ispublishedtrue
cristin.fulltextpreprint
cristin.qualitycode1


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