Challenges of SiC MOSFET Power Cycling Methodology
Chapter, Peer reviewed
Submitted version
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http://hdl.handle.net/11250/2582542Utgivelsesdato
2018Metadata
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- Publikasjoner fra CRIStin - SINTEF Energi [1633]
- SINTEF Energi [1757]
Originalversjon
20th European Conference on Power Electronics and Applications 2018Sammendrag
This paper investigates the power cycling methodology for reliability testing of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). Dedicated test benches were designed and built to study this issue. The results indicate that power cycling of SiC MOSFETs is affected by threshold voltage instability. A proposal for reducing the influence of the latter is also given. This is done by adding an additional gate pulse to the device under test, in order to achieve an average bias of zero during one cycle of the power cycling experiment. Challenges of SiC MOSFET Power Cycling Methodology