A Novel Scalable Decision Tree Implementation on SoC Based FPGAs

Abstract

Machine learning algorithms are rapidly growing in predictive maintenance and condition monitoring systems for valuable assets. Decision tree classification (DTC) is one of popular methods in condition monitoring systems based on vibration analysis. Due to big amount of data coming out from vibration sensors, the processing should be done on edge close to the sensors. DTC can reach high accuracy but at the same time it is computationally intensive and edge processors are not able to run it so fast. There are some FPGA implementation that work fine for small datasets but have issues when there is a real big dataset that needs deep trees. In this paper we introduce our new method of Decision Tree (DT) implementation on SoC based FPGAs. We have shown that using a combination of FPGA and processor, the DT can be implemented much faster and more scalable for trees with depth up to 50. We have used Vivado HLS to implement our DTs and connected them to the processor of SoC via AXI interfaces. We have shown that our implementation gains up to 2.27x speed up comparing with only software implementation.